Author:
Gope J.,Bhadra S.,Chanda S.,Sarkar M.,Pal S.,Rai A.
Cited by
3 articles.
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1. Design of Three-valued Logic Half-Subtractor using GNRFET;2023 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI);2023-04-19
2. MVL Sequential Circuits;Beyond Binary Memory Circuits;2022
3. A review on the design of ternary logic circuits*;Chinese Physics B;2021-12-01