Dual Source Vertical TFET Channel Overlapped Structure with Enhanced RF/Analog Performance for Low-Power- Applications
Author:
Affiliation:
1. Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Lucknow,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10335696/10335697/10335835.pdf?arnumber=10335835
Reference20 articles.
1. Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers
2. Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
3. Improved Drain Current Characteristics of HfO2/SiO2 Dual Material Dual Gate Extension on Drain Side-TFET
4. Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level
5. Design and Investigation of a Novel Gate-All-Around Vertical Tunnel FET with Improved DC and Analog/RF Parameters
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