VLSI Implementation of Area-Error Optimized Compressor-Based Modified Wallace Tree Multiplier
Author:
Affiliation:
1. Sree Vidyanikethan Engineering College,Department of ECE,Tirupati,India
2. Christ Deemed to be University,Department of EEE,Bangalore,India
3. Dr.Mahalingam College of Technology,Department of EEE,Pollachi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10335696/10335697/10335812.pdf?arnumber=10335812
Reference13 articles.
1. Approximate multipliers based on a novel unbiased approximate 4-2 compressor
2. Low area ASIC implementation of LUT–CLA–QTL architecture for cryptography applications
3. Design of an Energy-Efficient Approximate Compressor for Error-Resilient Multiplications
4. Design of Ultra-Low Power Consumption Approximate 4–2 Compressors Based on the Compensation Characteristic
5. Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors
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