Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors-Reference-Cited by-同舟云学术

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Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors

Published:2005-02 Issue:2 Volume:16 Page:99-112
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Bambha N.K.,Bhattacharyya S.S.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx5/71/30026/01374852.pdf?arnumber=1374852

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Genetic Node-Mapping Methods for Rapid Collective Communications;IEICE Transactions on Information and Systems;2020-01-01

2. Design automation for application-specific on-chip interconnects: A survey;Integration;2016-01

3. Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling;Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems;2015-06

4. Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects;ACM Transactions on Embedded Computing Systems;2015-05-21

5. Improving performance of multi-core NUCA coherent systems using NoC-assisted mechanisms;The Journal of Supercomputing;2012-06-09

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