Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA-Reference-Cited by-同舟云学术

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Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA

Published:2021-09-20 Issue: Volume: Page:
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Container-title:2021 IEEE High Performance Extreme Computing Conference (HPEC)
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Author:

Wijeratne Sasindu,Kannan Rajgopal,Prasanna Viktor

Funder

National Science Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9622740/9622741/09622851.pdf?arnumber=9622851

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

2. OptiCPD: Optimization For The Canonical Polyadic Decomposition Algorithm on GPUs;2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2023-05

3. Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA;Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2023-02-12

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