Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking-Reference-Cited by-同舟云学术

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Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking

Published:2022-02 Issue: Volume: Page:
ISSN:
Container-title:2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID)
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Author:

Rahaman Habibur¹,Chattopadhyay Santanu²,Sengupta Indranil¹,Das Debesh K.³,Bhattacharya Bhargab B.¹

Affiliation:

1. Indian Institute of Technology,Dept. of Computer Science and Engineering,Kharagpur,India

2. Indian Institute of Technology,Dept. of Electronics and Electrical Communication Engg.,Kharagpur,India

3. Jadavpur University,Dept. of Computer Science and Engineering,Kolkata,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9885796/9885734/09885877.pdf?arnumber=9885877

Reference23 articles.

1. Sequential test generation and synthesis for testability at the register-transfer and logic levels

2. A protocol test generation procedure

3. Testing Software Design Modeled by Finite-State Machines

4. Fault Detection for Sequential Machines by Transitions Tours;naito;Proc IEEE Fault-Tolerant Comput Symp,1981

5. Automatic State-Based Test Generation Using Genetic Algorithms;lefticaru;Proc IEEE Inti Symp on Symbolic and Numeric Algorithmsfor Scientific Computing,2008

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