Wafer level and flip chip design through solder prediction models and validation-Reference-Cited by-同舟云学术

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Wafer level and flip chip design through solder prediction models and validation

Published:2001 Issue:4 Volume:24 Page:650-654
ISSN:1521-3331
Container-title:IEEE Transactions on Components and Packaging Technologies
language:
Short-container-title:IEEE Trans. Comp. Packag. Technol.

Author:

Li L.,Yeung B.H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/6144/21029/00974956.pdf?arnumber=974956

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study of shear locking effect on 3D solder joint reliability analysis;Journal of Mechanics;2022

2. Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging;Micromachines;2021-03-10

3. Fatigue Life and Reliability Analysis of Electronic Packages Under Thermal Cycling and Moisture Conditions;Proceedings of the Institute of Industrial Engineers Asian Conference 2013;2013

4. Development and Experimental Validation of a 3-D Solder Self-Alignment Model for Alignment Accuracy Prediction of Flip-Chip Assembly;IEEE Transactions on Components, Packaging and Manufacturing Technology;2011-10

5. Predicting the Liquid Formation for the Solder Joints in Flip Chip Technology;Journal of Electronic Packaging;2005-09-29

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