Multi-Stage Comparator Progressive Offset Cancellation f or SAR ADC
Author:
Affiliation:
1. Peking University,Shenzhen Graduate School,Shenzhen,China
2. Southeast University,School of Electronic Science and Engineering,Nanjing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10210847/10211258/10211459.pdf?arnumber=10211459
Reference7 articles.
1. Design of cmos ring vco for pll based frequency synthesizer;sachdeva;International Journal of Electrical and Electronic Engineering & Telecommunications,2016
2. A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS
3. A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques
4. Reduce power consumption for digital cmos circuits using dvts algoritham;rajeshkumar;International Journal of Electrical and Electronic Engineering & Telecommunications,2015
5. Design of comparator with offset cancellation for 12-bit 1.6MS/s successive approximation ADC
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