Ternary multiplication circuits using 4-input adder cells and carry look-ahead-Reference-Cited by-同舟云学术

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Ternary multiplication circuits using 4-input adder cells and carry look-ahead

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Container-title:Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)
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Author:

Herrfeld A.,Hentschke S.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/6333/16922/00779713.pdf?arnumber=779713

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Ternary Half Adder Using DGFET Technology for Low Power Applications;2023 3rd International Conference on Energy, Power and Electrical Engineering (EPEE);2023-09-15

2. Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic;2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL);2021-05

3. The design of ternary logic units on the basis of the standard MOS technology;Russian Microelectronics;2009-05

4. On MultiModuli residue number systems with moduli of forms r/sup a/, r/sup b/-1, r/sup c/+1;IEEE Transactions on Circuits and Systems I: Regular Papers;2005-07

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