Effect of Deep Level Traps on the Performance of E-Mode Recessed Gate GaN Double-Channel MOS-HEMT
Author:
Affiliation:
1. Bangladesh University of Engineering and Technology (BUET),Department of Electrcal and Electronic Engineering,Dhaka,Bangladesh
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9829529/9829533/09829592.pdf?arnumber=9829592
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4. Analytical Drain Current Model for Amorphous and Polycrystalline Silicon Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States;he;2018 9th Int Conf Comput Aided Des Thin-Film Transistor Technol CAD-TFT 2018,2019
5. An etch-stop barrier structure for GaN high-electron-mobility transistors;lu;IEEE Electron Device Lett,2013
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