An Adaptive Digital PLL Based on BBPFD Transition Probability
Author:
Affiliation:
1. Graduate Institute of Electronics Engineering, National Taiwan University,Department of Electrical Engineering,Taipei,Taiwan
Funder
National Taiwan University
Ministry of Science and Technology, Taipei, Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9768045/9768046/09768066.pdf?arnumber=9768066
Reference16 articles.
1. An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection
2. A 320-fs RMS Jitter and – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC
3. A-240dB-FoM jitter and ?115dBc/Hz PN @ 100kHz, 7.7GHz ring-DCO-based digital PLL using P/I-gain co-optimization and sequence-rearranged optimally spaced TDC for flicker-noise reduction;lee;IEEE Int Solid-State Circuits Conf (ISSCC),2020
4. An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique
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