Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si/sub 1-x/Gex source/drain-Reference-Cited by-同舟云学术

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Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si/sub 1-x/Gex source/drain

Published:2000-09 Issue:9 Volume:21 Page:448-450
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Hsiang-Jen Huang ,Kun-Ming Chen ,Chun-Yen Chang ,Liang-Po Chen ,Guo-Wei Huang ,Tiao-Yuan Huang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/18702/00863107.pdf?arnumber=863107

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