Performance and Energy Implications of Many-Core Caches for Throughput Computing

Author:

Hughes C J,Changkyu Kim ,Yen-Kuang Chen

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. NUBA: Non-Uniform Bandwidth GPUs;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2023-01-27

2. Adaptive memory-side last-level GPU caching;Proceedings of the 46th International Symposium on Computer Architecture;2019-06-22

3. Energy Consumption Improvement of Shared-Cache Multicore Clusters Based on Explicit Simultaneous Multithreading;2017 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW);2017-10

4. DASC-DIR: a low-overhead coherence directory for many-core processors;The Journal of Supercomputing;2014-11-05

5. A SURVEY OF TECHNIQUES FOR MANAGING AND LEVERAGING CACHES IN GPUs;Journal of Circuits, Systems and Computers;2014-06-18

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