A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel

Author:

Fettweis Gerhard,Hassler Mattis,Wittig Robert,Matus Emil,Damjancevic Stefan,Haas Sebastian,Pauls Friedrich,Nam Seungseok,Grigoryan Nairuhi

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Trust-minimized Integration of Third-Party Intellectual Property Cores;2023 20th International SoC Design Conference (ISOCC);2023-10-25

2. Trustworthy Computing for O-RAN: Security in a Latency-Sensitive Environment;2022 IEEE Globecom Workshops (GC Wkshps);2022-12-04

3. A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems;2022 32nd International Conference on Field-Programmable Logic and Applications (FPL);2022-08

4. A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI;2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2022-07

5. AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors;IEEE Access;2022

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