High-performance optimization of SM4-GCM based on FPGA
Author:
Affiliation:
1. School of Information Engineering Zhengzhou University,Zhengzhou,China
2. State Key Laboratory of Mathmatical Engineering and Advanced Computing,Zhengzhou,China
3. Schoo of Information Engineering Zhengzhou University,Zhengzhou,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10013311/10013093/10013330.pdf?arnumber=10013330
Reference18 articles.
1. Implementation of SM4 on FPGA: Trade-Off Analysis between Area and Speed
2. Improving the performance of multi-mode SM4 block cipher[J];hu;International Journal of Performability Engineering,2019
3. Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m)
4. Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs
5. Efficient implementation of the Galois Counter Mode using a carry-less multiplier and a fast reduction algorithm
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1. A 128-Gbps Pipelined SM4 Circuit With Dual DPA Attack Countermeasures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06
2. Unified Lossless-Throughput Architecture for AES and SM4 Encryption with Changeable Keys;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. Low Power S-Box Architecture for SM4 Algorithm;2024 5th International Seminar on Artificial Intelligence, Networking and Information Technology (AINIT);2024-03-29
4. A novel SM4 cryptographic architecture against higher order power analysis attacks;International Journal of Circuit Theory and Applications;2024-01-31
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