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Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation

  • Published:2019-08 Issue:8 Volume:38 Page:1385-1398
  • ISSN:0278-0070
  • Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • language:
  • Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Tao JunORCID,Su Yangfeng,Zhou Dian,Zeng XuanORCID,Li XinORCID

Funder

National Major Science and Technology Special Project of China

National Key Research and Development Program of China

National Natural Science Foundation of China

Recruitment Program of Global Experts

National Science Foundation

Fudan University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Machine learning driven global optimisation framework for analog circuit design;Microelectronics Journal;2024-09

2. A Survey on Smart Optimisation Techniques for 6G-oriented Integrated Circuits Design;Mobile Networks and Applications;2024-05-16

3. Hierarchical Optimization based on Partial Performance Tradeoff Modeling Method for Large Scale Analog Circuits;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

4. Graph Based Systematic Synthesis Procedure of gm-C Filter;2023 7th International Conference on Electronics, Communication and Aerospace Technology (ICECA);2023-11-22

5. Novel Methods for Improved Particle Swarm Optimization in Designing the Bandgap Reference Circuit;IEEE Access;2023
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