Assertion Ranking Using RTL Source Code Analysis-Reference-Cited by-同舟云学术

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Assertion Ranking Using RTL Source Code Analysis

Published:2020-08 Issue:8 Volume:39 Page:1711-1724
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Pal Debjit^ORCID,Offenberger Spencer,Vasudevan Shobha^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/9142465/08732465.pdf?arnumber=8732465

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. VeriBug: An Attention-Based Framework for Bug Localization in Hardware Designs;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

2. LFPS: Learned Formal Proof Strengthening for Efficient Hardware Verification;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

3. Detection of fraudulent marketing of consumer product in social networking services;Journal of Intelligent & Fuzzy Systems;2023-08-24

4. An automated method for mining high-quality assertion sets;Microprocessors and Microsystems;2023-03

5. Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12

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