Fast Timing-Model Independent Buffered Clock-Tree Synthesis-Reference-Cited by-同舟云学术

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Fast Timing-Model Independent Buffered Clock-Tree Synthesis

Published:2012-09 Issue:9 Volume:31 Page:1393-1404
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Shih Xin-Wei,Chang Yao-Wen

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/6269957/06269968.pdf?arnumber=6269968

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs;2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2023-06-20

2. Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization;IEEE Access;2023

3. Performance Analysis on Skew Optimized Clock Tree Synthesis;2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT);2022-12-26

4. An Approximate Symmetry Clock Tree Design with Routing Topology Prediction;2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS);2021-08-09

5. Clock Power Reduction Using NDR Routing;Lecture Notes in Electrical Engineering;2021

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