Author:
Chaix Fabien,Ailamakis Georgios,Vavouris Theocharis,Damianakis Astrinos,Katevenis Manolis,Mavroidis Iakovos,Ioannou Aggelos,Kossifidis Nikolaos,Dimou Nikolaos,Ieronymakis Giorgos,Marazakis Manolis,Papaefstathiou Vassilis,Flouris Vassilis,Ligerakis Mihailis
Cited by
7 articles.
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1. Low-latency Communication in RISC-V Clusters;Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region;2024-01-18
2. The Prism Bridge: Maximizing Inter-Chip AXI Throughput in the High-Speed Serial Era;IEEE Access;2023
3. Preconditioned Conjugate Gradient Acceleration on FPGA-Based Platforms;Electronics;2022-09-24
4. Performance assessment of FPGAs as HPC accelerators using the FPGA Empirical Roofline;2021 31st International Conference on Field-Programmable Logic and Applications (FPL);2021-08
5. UNILOGIC;ACM Transactions on Reconfigurable Technology and Systems;2020-10