Hysteresis cycle in the latch-up characteristic of wide CMOS structures-Reference-Cited by-同舟云学术

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Hysteresis cycle in the latch-up characteristic of wide CMOS structures

Published:1988-05 Issue:5 Volume:9 Page:214-216
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Selmi L.,Sangiorgi E.,Crisenza G.,Re D.,Ricco B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx1/55/46/00000694.pdf?arnumber=694

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A study of latch-up hysteresis in n-well CMOS by means of I–V characteristics and photoemission techniques;Solid-State Electronics;1993-04

2. Latch-up in CMOS circuits: A review;European Transactions on Telecommunications;1990-05

3. Three-dimensional effects in dynamically triggered CMOS latchup;IEEE Transactions on Electron Devices;1989-09

4. New observance and analysis of various guard-ring structures on latch-up hardness by backside photo emission image;2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.

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