Design and performance evaluation of a reconfigurable Delta MIN for MPSOC
Author:
Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4489831/4497639/04497674.pdf?arnumber=4497674
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs;Applied Sciences;2023-12-20
2. Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs;Advanced Information Networking and Applications;2020
3. Flattening: An efficient approach to improving the performance of conventional MINs;Microelectronics Journal;2015-10
4. Design and implementation of Multistage Interconnection Networks using Quantum-dot Cellular Automata;Microelectronics Journal;2011-06
5. A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture;Reconfigurable Embedded Control Systems;2011
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