Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V-Reference-Cited by-同舟云学术

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Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V

Published:2020-12 Issue:12 Volume:39 Page:4453-4465
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

De Asmit^ORCID,Basu Aditya,Ghosh Swaroop^ORCID,Jaeger Trent

Funder

Semiconductor Research Corporation

National Science Foundation

DARPA Young Faculty Award

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

https://ieeexplore.ieee.org/ielam/43/9265421/9051971-aam.pdf

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09

2. $$\mu $$IPS: Software-Based Intrusion Prevention for Bare-Metal Embedded Systems;Lecture Notes in Computer Science;2024

3. Security Challenges Faced by RISC-V open-source Processors and its Security Features: A Survey;2023 25th International Multitopic Conference (INMIC);2023-11-17

4. A Survey on Thwarting Memory Corruption in RISC-V;ACM Computing Surveys;2023-09-14

5. CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core;2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2023-05-01

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