Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning-Reference-Cited by-同舟云学术

Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning

Published:2022-12 Issue:12 Volume:41 Page:5138-5151
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Zhao Zhenxin¹^ORCID,Zhang Lihong¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John’s, NL, Canada

Funder

Natural Sciences and Engineering Research Council of Canada

Canada Foundation for Innovation

Provincial Government of Newfoundland and Labrador

Memorial University of Newfoundland

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/9956950/09718525.pdf?arnumber=9718525

Reference34 articles.

1. Layout-dependent effects aware gm/ID-based many-objective sizing optimization for analog integrated circuits;liao;Proc IEEE Int Symp Circuits Syst (ISCAS),2018

2. Analog module placement realizing symmetry constraints based on a radiation decoder;zhang;Proc IEEE Int Midwest Symp Circuits Syst,2004

3. Deep Reinforcement Learning: A Brief Survey

4. Fast parasitic-aware synthesis methodology for high-performance analog circuits

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