EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
2. Circuit Research Lab, Intel Labs, Hillsboro, OR, USA
3. Security and Privacy Research, Intel Labs, Hillsboro, OR, USA
Funder
National Science Foundation
Intel Corporation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
https://ieeexplore.ieee.org/ielam/43/9928799/9684545-aam.pdf
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4. Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection
5. A 10nm high performance and low-power CMOS technology featuring $3^{rd}$ generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects;auth;Proc IEEE Int Electron Devices Meeting (IEDM),2017
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