Aging Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort-Reference-Cited by-同舟云学术

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Aging Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

Published:2022 Issue: Volume: Page:1-1
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Acharya Lomash Chandra¹^ORCID,Sharma Arvind Kumar²^ORCID,Mishra Neeraj³^ORCID,Singh Khoirom Johnson¹^ORCID,Dargupally Mahipal¹^ORCID,Shabarish Nayakanti Sai¹,Mandal Ajoy⁴,Ramakrishnan Venkatraman⁴,Dasgupta Sudeb¹^ORCID,Bulusu Anand¹^ORCID

Affiliation:

1. Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, India

2. Imec, Belgium

3. KU Leuven, Belgium

4. Texas Instruments, Bengaluru, India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/6917053/09996090.pdf?arnumber=9996090

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Complete Timing Model of ECSM Lookup Table for CMOS Inverter;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

2. Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03

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