Author:
Lee Siang-Yun,Riener Heinz,Mishchenko Alan,Brayton Robert K.,De Micheli Giovanni
Funder
Schweizerischer Nationalfonds zur Frderung der Wissenschaftlichen Forschung
cole Polytechnique Fdrale de Lausanne
SRC
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
2. Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
3. Logic Synthesis for Emerging Technologies;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
4. External Don’t Cares in Logic Synthesis;Advanced Boolean Techniques;2023
5. Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17