Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System
Author:
Affiliation:
1. Nitte Meenakshi Institute of Technology,Bangalore,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9702710/9702711/09702732.pdf?arnumber=9702732
Reference20 articles.
1. Congestion driven quadratic placement
2. TACO
3. Gate-size selection for standard cell libraries
4. Gate sizing in MOS digital circuits with linear programming
5. A class of min-cut placement algorithms
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