FPGA-Based Label Processor for Low Latency and Large Port Count Optical Packet Switches
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Atomic and Molecular Physics, and Optics
Link
http://xplorestaging.ieee.org/ielx5/50/6308750/06289332.pdf?arnumber=6289332
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. 25.6 Tbps Capacity and Sub-µsec Latency Switching for DataCenters Using >1000-Port Optical Packet Switch Architectures;IEEE Journal of Selected Topics in Quantum Electronics;2021-03
2. Experimental demonstration of an ultra-low latency control plane for optical packet switching in data center networks;Optical Switching and Networking;2019-04
3. High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture [Invited];Journal of Optical Communications and Networking;2018-06-12
4. HiFOST: A Scalable and Low-Latency Hybrid Data Center Network Architecture Based on Flow-Controlled Fast Optical Switches;Journal of Optical Communications and Networking;2018-05-04
5. Multicast-Enabling Optical Switch Design Employing Si Buffering and Routing Elements;IEEE Photonics Technology Letters;2018-04-15
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