Virtual PCB Layout Prototyping: Importance of Modeling Gate Driver and Parasitic Capacitances-Reference-Cited by-同舟云学术

Virtual PCB Layout Prototyping: Importance of Modeling Gate Driver and Parasitic Capacitances

Published:2022-09-01 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Design Methodologies Conference (DMC)
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Author:

Nagel Michel¹,Race Salvatore¹,Kovacevic-Badstuebner Ivana¹,Ziemann Thomas¹,Grossner Ulrike¹

Affiliation:

1. ETH Zurich,Advanced Power Semiconductor Laboratory,Zurich,Switzerland

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9906465/9906466/09906542.pdf?arnumber=9906542

Reference7 articles.

1. A Component Manipulation Algorithm to Enable Design Automation of Power Electronic PCBs

2. PowerSynth Integrated CAD flow for High Density Power Modules

3. Towards Digital Twins for the Optimization of Power Electronic Switching Cells with Discrete SiC Power MOSFETs;race;Proc of International Exhibition and Conference for Power Electronics Intelligent Motion Renewable Energy and Energy Management (PCIM Europe),2022

4. A flexible test bench for power semiconductor switching loss measurements

5. Tools for Broadband Electromagnetic Modeling of Power Semiconductor Packages and External Circuit Layouts

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1. Influence of the r_ds,on temperature dependency of SiC MOSFETs on the optimal switching cell mechanical layout;2023 25th European Conference on Power Electronics and Applications (EPE'23 ECCE Europe);2023-09-04

2. High-frequency All SiC Improved Quadratic Boost Converter;2023 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia);2023-08-27