1. A 224 Gb/s DAC-based PAM-4 transmitter with 8-tap FFE in 10 nm CMOS;kim;IEEE ISSCC Dig Tech Papers,2021
2. F5: 56 Gb/s to 112 Gb/s and beyond–design challenges and solutions in wireline communications;joy;IEEE ISSCC Dig Tech Papers,2019
3. 112 G PAM 4/56 G NRZ interconnect design for high channel count packages;liu;Proc IEEE 27th Conf Electr Perform Electron Packag Syst (EPEPS),2018
4. Crosstalk challenge and mitigation through strategic pin placement for 25 Gbps and beyond;dong;Proc IEEE 65th Electron Compon Technol Conf (ECTC),2015
5. Differential Crosstalk Mitigation in the Pin Field Area of SerDes Channel With Trace Routing Guidance