A 128 Gb/s 7-Tap FIR Filter in 130 nm SiGe BiCMOS for High-Speed Channel Equalization
Author:
Affiliation:
1. IHP–Leibniz-Institute für Innovative Mikroelektronik, Frankfurt (Oder), Germany
2. FG Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, Germany
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/9944983/10042139/09928070.pdf?arnumber=9928070
Reference10 articles.
1. A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology
2. A 2.4-$\hbox{V} _{\rm pp}$ 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies
3. A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55 nm BiCMOS;verplaetse;Proc IEEE Custom Integr Circuits Conf (CICC),2021
4. All-Analog Adaptive Equalizer for Coherent Data Center Interconnects
5. A CMOS Finite Impulse Response Filter With a Crossover Traveling Wave Topology for Equalization up to 30 Gb/s
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