A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator-Reference-Cited by-同舟云学术

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A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator

Published:2023-10-25 Issue: Volume: Page:19-20
ISSN:
Container-title:2023 20th International SoC Design Conference (ISOCC)
language:
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Author:

An Gwangmyeong¹,Yoon Juneho²,Kim Taeho¹,Jang Hyunsu¹,Park Myeongju¹,Kim Bongsu¹,An Jongchan¹,Song Junyoung¹

Affiliation:

1. Incheon National University,Department of Electronics Engineering,Incheon,South Korea

2. Bellarmine College Preparatory,California,USA

Funder

Technology Development

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395912/10395932/10395942.pdf?arnumber=10395942

Reference5 articles.

1. A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement

2. Capacitor-Less Dual-Mode All-Digital LDO With ΔΣ-Modulation-Based Ripple Reduction

3. A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation

4. All-Digital Low-Dropout Regulator with Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits

5. A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications

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