Impact of High-$\kappa$ Offset Spacer in 65-nm Node SOI Devices-Reference-Cited by-同舟云学术

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Impact of High-$\kappa$ Offset Spacer in 65-nm Node SOI Devices

Published:2007-03 Issue:3 Volume:28 Page:238-241
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Ma Ming-Wen,Wu Chien-Hung,Yang Tsung-Yu,Kao Kuo-Hsing,Wu Woei-Cherng,Wang Shui-Jinn,Chao Tien-Sheng,Lei Tan-Fu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/4114563/04114575.pdf?arnumber=4114575

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1. Study the Impact of ZrO2 High-k Dielectrics Gate Material on FD-SOI and PD-SOI MOSFET;Lecture Notes in Electrical Engineering;2022-09-04

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3. Device Investigation of Nanoplate Transistor With Spacer Materials;IEEE Transactions on Electron Devices;2019-01

4. Si 3 N 4 :HfO 2 dual‐k spacer bulk planar junctionless transistor for mixed signal integrated circuits;IET Circuits, Devices & Systems;2018-08-30

5. Comparison of dual- k spacer and single- k spacer for single NWFET and 3-stack NWFET;Solid-State Electronics;2018-02

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