Partitioning and pipelining for performance-constrained hardware/software systems

Author:

Bakshi S.,Gajski D.D.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Investigation on Distributed Real-Time Embedded System;Social Networking and Computational Intelligence;2020

2. Synthesizing distributed pipelining systems with timing constraints via optimal functional unit assignment and communication selection;Journal of Computational Science;2018-05

3. Optimal functional unit assignment and voltage selection for pipelined MPSoC with guaranteed probability on time performance;ACM SIGPLAN Notices;2017-09-14

4. Optimal functional unit assignment and voltage selection for pipelined MPSoC with guaranteed probability on time performance;Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems;2017-06-21

5. Optimal functional-unit assignment and buffer placement for probabilistic pipelines;Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis;2016-10

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