A 6.7–3.6-pJ/b 0.63–7.5-Gb/s Rapid On/Off Clock and Data Recovery With <55-ns Turn-On Time-Reference-Cited by-同舟云学术

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A 6.7–3.6-pJ/b 0.63–7.5-Gb/s Rapid On/Off Clock and Data Recovery With <55-ns Turn-On Time

Published:2024 Issue: Volume:7 Page:14-17
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Bandarupalli Jaya Deepthi¹^ORCID,Saxena Saurabh¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai, India

Funder

Early Carrer Research Award from SERB, GoI

Center of Excellence in RF, Analog, and Mixed Signal ICs (CERAMIC) at IIT Madras

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/10359146/10330728.pdf?arnumber=10330728

Reference15 articles.

1. The Case for Energy-Proportional Computing

2. Energy proportional datacenter networks

3. A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

4. Multi-gigabit-rate clock and data recovery based on blind oversampling

5. A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

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