A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS-Reference-Cited by-同舟云学术

A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS

Published:2024 Issue: Volume:7 Page:50-53
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Ma Shuaizhe¹^ORCID,Yin Zhenyu¹,Ran Nianquan¹,Xia Yifei¹^ORCID,Yang Ruixuan¹^ORCID,Yu Chuanhao¹,Xu Songqin¹,Wang Binhao²^ORCID,Qi Nan³^ORCID,Zhang Bing¹^ORCID,Shi Jingbo⁴,Gui Xiaoyan¹^ORCID,Geng Li¹^ORCID,Li Dan¹^ORCID

Affiliation:

1. Faculty of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an, China

2. Institute of Optics and Precision Mechanics, University of Chinese Academy of Sciences, Xi’an, China

3. Institute of Semiconductors, University of Chinese Academy of Sciences, Beijing, China

4. State Key Laboratory of Information Photonics and Optical Communications, School of Integrated Circuits, Beijing University of Posts and Telecommunications, Beijing, China

Funder

Natural Science Foundation of China

National Key Research and Development Plan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8011414/10359146/10384640.pdf?arnumber=10384640

Reference10 articles.

1. A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/$\lambda$ PAM-4 Optical Links

2. A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS

3. A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with −14dBm Optical Sensitivity in 16nm CMOS

4. A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

5. 34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers