Dual-Mode Conversion Gating, Comparator Merging, and Reference-Less Calibration for 2.7× Energy Reduction in SAR ADCs Under Low-Activity Inputs-Reference-Cited by-同舟云学术

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Dual-Mode Conversion Gating, Comparator Merging, and Reference-Less Calibration for 2.7× Energy Reduction in SAR ADCs Under Low-Activity Inputs

Published:2023 Issue: Volume:6 Page:57-60
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Ali Karim¹^ORCID,Teo J. H.¹^ORCID,Sarkar S.¹^ORCID,Alioto M.¹^ORCID

Affiliation:

1. ECE Department, National University of Singapore, Cluny Road, Singapore

Funder

IAF

Agency for Science, Technology and Research

SOITEC

NXP

National University of Singapore through FD-fAbrICS

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/10016898/10048489.pdf?arnumber=10048489

Reference11 articles.

1. A 3–10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC

2. A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching

3. A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications

4. A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications

5. 11.3 A 10b 0.6nW SAR ADC with data-dependent energy savings using LSB-first successive approximation;yaul;ISSCC Dig Tech Papers,2014

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reinforcement-Learning-Based Successive Approximation Algorithm;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Design of Self-Calibration Comparator for 12-Bit SAR ADCs;Electronics;2023-05-18

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