Determination of trapped oxide charge in flash EPROMs and MOSFETs with thin oxides
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx1/55/4972/00192784.pdf?arnumber=192784
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. GIDL current degradation in LDD nMOSFET under hot hole stress;Journal of Semiconductors;2011-11
2. Minimized Constrains for Lateral Profiling of Hot-Carrier-Induced Oxide Charge and Interface Traps in MOSFETs;IEEE Electron Device Letters;2004-02
3. Radiation effects and hardening of MOS technology: devices and circuits;IEEE Transactions on Nuclear Science;2003-06
4. Single-wafer polysilicon engineering for the improvement of over erase in a 0.18-μm floating-gate flash memory;IEEE Transactions on Semiconductor Manufacturing;2003-05
5. Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/ device;IEEE Electron Device Letters;2001-11
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