Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN–Alumina–Nitride–Vacuum–Silicon Structure-Reference-Cited by-同舟云学术

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Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN–Alumina–Nitride–Vacuum–Silicon Structure

Published:2011-08 Issue:8 Volume:32 Page:1095-1097
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Wu Chun-Yu,Liu Yen-Ting,Liao Ta-Chuan,Yu Ming H.,Cheng Huang-Chung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/5961166/05940987.pdf?arnumber=5940987

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Technology demonstration of a novel poly-Si nanowire thin film transistor;Chinese Physics B;2016-11

3. 3D Memory Using Double-Gate, Folded, TFT, and Stacked Crystal Silicon;Vertical 3D Memory Technologies;2014-07-25

4. Improved programming and erasing speeds of poly-Si flash memory device by HfO2/Si3N4 bandgap-engineered trapping layer;Microelectronic Engineering;2013-09

5. Quasi-vertical multi-tooth thin film transistors based on low-temperature technology (T⩽600°C);Solid-State Electronics;2013-01

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