Design of High Speed Time – Interleaved SAR Analog to Digital Converter-Reference-Cited by-同舟云学术

Design of High Speed Time – Interleaved SAR Analog to Digital Converter

Published:2022-04-21 Issue: Volume: Page:
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Container-title:2022 6th International Conference on Devices, Circuits and Systems (ICDCS)
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Author:

Atchaya A Josephine¹,Shylu Sam D.S.¹,Herinsha A J¹,Mahendra Vignesh T¹

Affiliation:

1. Karunya Institute of Technology and Sciences,Department of Electronics and Communication Engineering,Coimbatore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9780660/9780663/09780703.pdf?arnumber=9780703

Reference24 articles.

1. Maximum Likelihood Estimation-Based SAR ADC

2. A 1.8V 22mW 10 bit 165 MSPS Pipelined ADC for Video Applications;shylu;WSEAS Transactions on Circuits and Systems,2014

3. Design of 12 Bit 100MS/s Low Power Delta Sigma ADC Using Telescopic Amplifier;shylu;Proceedings of the 4th International Conference on Devices Circuits and Systems ICDCS 20187,2019

4. A 10-Bit 5 MS / s VCOSAR ADC;xie,2019

5. A Second-Order NoiseShaping SAR ADC Using Two Passive;zhang,2021

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