Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers-Reference-Cited by-同舟云学术

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Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers

Published:2018-12 Issue:6 Volume:20 Page:578-592
ISSN:1229-2370
Container-title:Journal of Communications and Networks
language:
Short-container-title:J. Commun. Netw.

Author:

Zheng Ling,Qiu Zhiliang,Sun Shiyong,Pan Weitao,Gao Ya,Zhang Zhiyi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computer Networks and Communications,Information Systems

Link

http://xplorestaging.ieee.org/ielx7/5449605/8620635/08620641.pdf?arnumber=8620641

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Traffic Classification and Packet Scheduling Strategy with Deadline Constraints for Input-Queued Switches in Time-Sensitive Networking;Electronics;2024-02-02

2. Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric;Computer Networks;2021-10

3. DynaQ: Enabling Protocol-Independent Service Queue Isolation in Cloud Data Centers;IEEE Transactions on Cloud Computing;2021

4. Protocol-Independent Service Queue Isolation for Multi-Queue Data Centers;2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS);2020-11

5. Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches;International Journal of Communication Systems;2020-02-15

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