OPAL: On-the-go Physical Attack Lab to Evaluate Power Side-channel Vulnerabilities on FPGAs-Reference-Cited by-同舟云学术

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OPAL: On-the-go Physical Attack Lab to Evaluate Power Side-channel Vulnerabilities on FPGAs

Published:2021-11-30 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE Physical Assurance and Inspection of Electronics (PAINE)
language:
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Author:

Elnaggar Rana¹,Ray Sayak¹,Sabbagh Majid¹,Yuce Bilgiday¹,Wang Terry¹,Fung Jason¹

Affiliation:

1. Intel Corporation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9707693/9707694/09707701.pdf?arnumber=9707701

Reference21 articles.

1. ChipWhisperer: An opensource platform for hardware embedded security research;o’flynn;Constructive Side-Channel Analysis and Secure Design,2015

2. FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES

3. An inside job: Remote power analysis attacks on FPGAs

4. Voltage drop-based fault attacks on FPGAs using valid bitstreams

5. CPAmap: On the Complexity of Secure FPGA Virtualization, Multi-Tenancy, and Physical Design

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. A Survey on FPGA Cybersecurity Design Strategies;ACM Transactions on Reconfigurable Technology and Systems;2023-03-11

3. On-Chip Side-Channel Analysis of the Loop PUF;Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security;2022-11-07

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