Author:
Das S. R.,Banerji D. K.,Chattopadhyay A.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Cited by
29 articles.
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1. A novel architecture for conversion of binary to single digit double base numbers;ACM SIGARCH Computer Architecture News;2010-12-29
2. A New Generalized Reconfigurable Architecture for Digital Signal Processor;15th International Conference on Advanced Computing and Communications (ADCOM 2007);2007-12
3. Test-set embedding based on width compression for mixed-mode BIST;IEEE Transactions on Instrumentation and Measurement;2000-06
4. Algorithms for the Satisfiability (SAT) Problem;Handbook of Combinatorial Optimization;1999
5. Design of built-in test generator circuits using width compression;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1998