A CAD methodology for optimizing transistor current and sizing in analog CMOS design-Reference-Cited by-同舟云学术

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A CAD methodology for optimizing transistor current and sizing in analog CMOS design

Published:2003-02 Issue:2 Volume:22 Page:225-237
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:en
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Binkley D.M.,Hopper C.E.,Tucker S.D.,Moss B.C.,Rochelle J.M.,Foty D.P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/26375/01174097.pdf?arnumber=1174097

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