Constraint-Driven Test Scheduling for NoC-Based Systems
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Link
http://xplorestaging.ieee.org/ielx5/43/36103/01715430.pdf?arnumber=1715430
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1. Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip;Journal of Computer Science and Technology;2023-03-30
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3. Wrapper scan chain design algorithm for testing of embedded cores based on chaotic dragonfly algorithm;Evolutionary Intelligence;2020-10-22
4. ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC;Journal of Low Power Electronics and Applications;2019-06-17
5. Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing;ACM Transactions on Design Automation of Electronic Systems;2018-12-21
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