Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories-Reference-Cited by-同舟云学术

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Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Published:2008-11 Issue:11 Volume:27 Page:2053-2067
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Ben Jamaa Mohamed Haykel,Moselund Kirsten Emile,Atienza David,Bouvet Didier,Ionescu Adrian Mihai,Leblebici Yusuf,De Micheli Giovanni

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/4655545/04655554.pdf?arnumber=4655554

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Memristor-based combinational circuits: A design methodology for encoders/decoders;Microelectronics Journal;2014-01

2. Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique;IEEE Transactions on Nanotechnology;2011-07

3. Decoder Logic Design;Lecture Notes in Electrical Engineering;2011

4. Reliable Circuits Design with Nanowire Arrays;Nanoelectronic Circuit Design;2010-11-19

5. Design Technologies for Nanoelectronic Systems Beyond Ultimately Scaled CMOS;Nanosystems Design and Technology;2009

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