Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip-Reference-Cited by-同舟云学术

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Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Published:2009-08 Issue:8 Volume:28 Page:1251-1264
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Zhanglei Wang ,Chakrabarty K.,Seongmoon Wang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/5166543/05166602.pdf?arnumber=5166602

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Addressing Physically Aware Diagnosis Challenges in Hierarchical Core Based Designs;2023 IEEE International Test Conference India (ITC India);2023-07-23

2. Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms;Journal of Intelligent & Fuzzy Systems;2021-03-02

3. Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures;2018 IEEE International Test Conference in Asia (ITC-Asia);2018-08

4. Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression;JSTS:Journal of Semiconductor Technology and Science;2016-10-30

5. Case Study of Testing a SoC Design with Mixed EDT Channel Sharing and Channel Broadcasting;2016 IEEE 25th North Atlantic Test Workshop (NATW);2016-05

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