Secure Scan: A Design-for-Test Architecture for Crypto Chips

Author:

Yang B.,Wu K.,Karri R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 134 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. DefScan: Provably Defeating Scan Attack on AES-Like Ciphers;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. Hardware Security of Scan Chain;2023 IEEE 20th India Council International Conference (INDICON);2023-12-14

3. SASL-JTAG: A Light-Weight Dependable JTAG;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

4. Design-for-Testability and Its Impact on Logic Locking;Understanding Logic Locking;2023-09-23

5. A Lightweight Scan Architecture against the Scan-based Side-channel Attack;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2023-08-31

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