Evaluating the Optimal Self-Checking Carry Propagate Adder for Cryptographic Processor
Author:
Affiliation:
1. College of Science and Engineering Hamad Bin Khalifa University,Division of Information and Computing Technology,Doha,Qatar
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10008388/10008225/10008439.pdf?arnumber=10008439
Reference8 articles.
1. Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions;praghash;Wireless Personal Communications,2022
2. FPGA adders: performance evaluation and optimal design
3. A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization
4. Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration
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