Stacked circuit packaging method of multichip SiC MOSFET power modules for electrical performance improvement-Reference-Cited by-同舟云学术

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Stacked circuit packaging method of multichip SiC MOSFET power modules for electrical performance improvement

Published:2023-08-08 Issue: Volume: Page:1-5
ISSN:
Container-title:2023 24th International Conference on Electronic Packaging Technology (ICEPT)
language:
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Author:

Chen Hong¹,Qiu Xiangqi¹,Lu Pengfei¹,Wei Song²,Li Ruifeng³

Affiliation:

1. Guilin University of Electronic Technology,School of Mechanical and Electrical Engineering,Guilin,China

2. Guangxi Key Laboratory of Manufacturing System and Advanced Manufacturing Technology,School of Mechanical and Electrical,Guilin,China

3. Engineering Guilin University of Electronic Technology,Guilin,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10491594/10491891/10491944.pdf?arnumber=10491944

Reference6 articles.

1. Modeling and Analysis of SiC MOSFET Switching Oscillations

2. Parasitics in Power Electronic Modules: How parasitic inductance influences switching and how it can be minimized[C];Meisser

3. Characterization and Extraction of Power Loop Stray Inductance With SiC Half-Bridge Power Module

4. High Junction Temperature and Low Parasitic Inductance Power Module Technology for Compact Power Conversion Systems

5. A Wire-Bondless Packaging Platform for Silicon Carbide Power Semiconductor Devices

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